module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 

    int i;
    always @(posedge clk ) begin
        if(load)
            q <= data;
        else begin
            q[0]        <=  q[1] ^ 0;
            q[511]      <=  0 ^ q[510];
            for(i = 1; i<511;i=i+1)
                q[i] <= q[i - 1] ^ q[i + 1]; 
        end
    end

    /*
    always @(posedge clk) begin
		if (load)
			q <= data;	// Load the DFFs with a value.
		else begin
			// At each clock, the DFF storing each bit position becomes the XOR of its left neighbour
			// and its right neighbour. Since the operation is the same for every
			// bit position, it can be written as a single operation on vectors.
			// The shifts are accomplished using part select and concatenation operators.
			
			//     left           right
			//  neighbour       neighbour
			q <= q[511:1] ^ {q[510:0], 1'b0} ;
		end
	end
    */

endmodule
